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Float silu #7

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@alexfrater alexfrater commented Jul 30, 2024 •
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Floating point SiLU activation used in Graphast
Module Testbenches in Mase style

alexfrater added 30 commits June 12, 2024 13:48
@alexfrater
build bug fix
68089ce
@alexfrater
SIM Wave Windows
ba68158
@alexfrater
Temp Sys Path
dd7c3ca
@alexfrater
Fixed Weight Bank Bug
75a700d
@alexfrater
Simualtion Files and MLP model
63dcaca
@alexfrater
Debugging Full Simulation
40dcb98
@alexfrater
functions to save JIT model and graph
fd90818
@alexfrater
gnn model software integration in testbench
93b1b22
@alexfrater
9 jul
d1729b1
@alexfrater
nodeslot writeback monitor checker
a803129
@alexfrater
bug fix: empty weight FIFOs set to full and dumping undefined values …
dfabf34 
…when reset
@alexfrater
gating non-valid fp input values to prevent x-propogation
d50adb4
@alexfrater
fte writeback logic
239440c
@alexfrater
sim files
7539061
@alexfrater
bug generating 4 meshes
91c17d0
@alexfrater
bug generating 4 meshes 2
4e9905e
@alexfrater
aggregation feature write count - enable feature counts of arbitrary …
5b8f72b 
…length
@alexfrater
correct feature input order
31b372d
@alexfrater
testbench output data and size comparision
f3217d1
@alexfrater
fix wrong neigbour message address
38d071c
@alexfrater
allow writeback of non fully populated fte
f8227a7
@alexfrater
fast multiplication bug fix
aaa4300
@alexfrater
valid row fix for nodeslot count greater than tfe channel count (test…
5577d9a 
…bench passed)
@alexfrater
simulation edits
e2ebdac
@alexfrater
bug fix buffer slot reset after transform
7b80cb2
@alexfrater
fix bug last row of fte not reset
5b99d67
@alexfrater
backpressure enabled on agc feature aggregator and bug fix valid sign…
36fadb4 
…al feature aggregator
@alexfrater
mapping memory for varying feature widths in multi-layer mlp
f4c766c
@alexfrater
FTE writeback to HBM
a65f167
@alexfrater
multi layer weights mapping in sdk
6a3c4d9
alexfrater and others added 30 commits July 30, 2024 10:49
@alexfrater
brand publish
be024bb
@alexfrater
temp fixes from float_silu branch to allow verilator compilation
6800fc1
@alexfrater
Merge branch 'multilayer_models' of https://github.com/alexfrater/agile…
d66de93 
… into multilayer_models
@alexfrater
makefile
5d74b9a
@alexfrater
Merge branch 'edge_embeddings' into multilayer_models
a4c2de6 
Added edge embedding models
@alexfrater
multiple out messages locations
1953cb2
@alexfrater
added toml file
b16a713
@alexfrater
edge nodeslot programming
12a5bba
@alexfrater
model mapper class
c938809
@alexfrater
mapped edge embed layer memory
5e4fff6
@alexfrater
adj_list mapping
541efe3
@alexfrater
GraphTracer
b12715e
@alexfrater
edge embed model
02f5d87
@alexfrater
configure testbench for edge mebeddings - failing on edge update laye…
94e72ca 
…r (4)
@alexfrater
corrected edge mapping
062f430
@alexfrater
added ability to change nodeslots between layers - still bugs in edge…
a8c7123 
… embedding memory map
@alexfrater
edge embedding working - temporary aggregation pointers last layer
3aff44d
@alexfrater
edge embedding working - not tested entirely, MLP or GCN
48cd3da
@alexfrater
tested mlp and gcn
23f7e98
@alexfrater
interaction net node embedding
5ce3108
@alexfrater
edge aggregation
82de9bb
@alexfrater
working interaction net using work arounds
0be937d
@alexfrater
remove debug statements
bf5187b
@alexfrater
tested intergration with other models, improved benchmark
d4fdbdd
sending edge attr to cuda
26c39d0
@alexfrater
updates
8ab1883
@alexfrater
fixed monitors (apart from bm) and added state cycle profiling
d4811a1
@alexfrater
Merge branch 'main' of https://github.com/alexfrater/agile
598a8d8
@alexfrater
Merge branch 'main' into float_silu
fdb4ed1
@alexfrater
configurable logic block
4166df1
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@alexfrater