RISC-V MultiPrecision Processor Core

A synthesizable implementation of a RISC-V Single-Cycle Processor supporting both RV32I and RV64I base integer instruction sets. Designed using robust Register Transfer Level (RTL) principles, this project provides a clear, modular, and educational insight into computer architecture.

🌟 Key Features

• Multi-Precision Support: Full source code for both 32-bit (RV32I) and 64-bit (RV64I) architectures.
• Modular Design: Clean separation of Control Unit, Datapath, ALU, and Memory subsystems.
• Harvard Architecture: Separate Instruction and Data memories for simplified single-cycle access.
• Embedded Debugging: Exposes real-time internal states (PC, ALU Result, Instruction) for easy verification.
• GPIO Interface: Integrated General Purpose Input/Output for memory-mapped peripheral control.
• Synthesizable: Written in SystemVerilog, ready for FPGA deployment (Artix-7, Cyclone V, etc.).

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🏗️ High-Level Architecture

The processor executes instructions in a single clock cycle: Fetch $\rightarrow$ Decode $\rightarrow$ Execute $\rightarrow$ Memory $\rightarrow$ Writeback.

graph TD
    %% Styling
    classDef module fill:#e1f5fe,stroke:#01579b,stroke-width:2px;
    classDef memory fill:#fff3e0,stroke:#e65100,stroke-width:2px;
    
    subgraph Processor ["RISC-V Processor Core"]
        PC[Program Counter]:::module
        Control[Control Unit]:::module
        RegFile[Register File]:::module
        ALU[ALU]:::module
        ImmGen[Immediate Gen]:::module
        
        PC --> IM
        IM --> Control
        IM --> RegFile
        IM --> ImmGen
        
        RegFile --> ALU
        ImmGen --> ALU
        Control --> ALU
        Control --> RegFile
        Control --> DM
    end
    
    subgraph Memory ["Memory Subsystem"]
        IM[Instruction Memory]:::memory
        DM[Data Memory]:::memory
    end

    ALU --> DM
    DM --> RegFile
    ALU --> RegFile

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For a deep dive into the internal modules, signal flow, and decoder logic, implementation details, please read our Architecture Documentation:

• RV32I Walkthrough (32-bit)
• RV64I Walkthrough (64-bit)

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📂 Repository Structure

.
├── rv32i/                  # 32-bit RISC-V Implementation
│   └── src_modules/        # SystemVerilog source files
│
├── rv64i/                  # 64-bit RISC-V Implementation
│   └── src_modules/        # SystemVerilog source files
│
├── docs/                   # Documentation Resources
│   ├── ARCHITECTURE.md     # detailed Design Explanation
│   └── GETTING_STARTED.md  # Simulation & Setup Guide
│
├── CONTRIBUTING.md         # Guidelines for contributors
├── LICENSE                 # MIT License type
└── README.md               # Project Entry Point

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🚀 Usage & Simulation

This processor is designed to be simulator-agnostic. It works out-of-the-box with Xilinx Vivado, ModelSim, and Icarus Verilog.

Quick Start (Vivado)

1. Add all files from rv32i/src_modules (or rv64i/v) to your project.
2. Set CPU.sv as the top module.
3. Create a testbench instantiating CPU.
4. Run Behavioral Simulation.

For detailed step-by-step instructions, see the Getting Started Guide.

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🔧 Technical Specifications

Feature	RV32I	RV64I
Data Width	32-bit	64-bit
Address Space	4GB ($2^{32}$)	16EB ($2^{64}$)
Registers	32 x 32-bit	32 x 64-bit
Instruction Size	32-bit (Fixed)	32-bit (Fixed)
Est. Max Freq (Artix-7)	~80 MHz	~65 MHz

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🤝 Community & Contribution

We welcome contributions! Whether it's adding support for the M extension, optimizing the ALU, or improving documentation. Please review CONTRIBUTING.md before submitting a Pull Request.

� License

This project is open-source and available under the MIT License.