A structured reference and study guide drawn from real-world IC layout experience across analog, memory (SRAM), SoC, and general physical design. Built for reflection, interview prep, and helping others avoid the pain of learning everything the hard way.
Analog layout quality directly impacts performance, matching, and yield. Even with the best schematic, careless layout can destroy circuit precision.
- Analog Layout Interview Questions — Common interview prep topics and concept checks.
- Analog Block Glossary — Descriptions of common analog building blocks.
Core principles to remember:
- Matching & Symmetry — Matched devices should share identical surroundings: same distance to wells, same STI boundaries, mirrored guard rings.
- Placement Techniques — Use common-centroid or interdigitated arrangements to average out gradients and stress effects.
- Guard Rings & Isolation — Surround sensitive devices with mirrored guard rings; ensure equal proximity on all sides to avoid imbalance.
- ESD & Latch-up Prevention — Follow foundry guard ring/tap spacing rules to protect inputs and maintain substrate bias control.
- Sensitive Node Handling — Shield high-impedance nodes from noisy routing and keep them short to minimize parasitic coupling.
SRAM layout requires strict adherence to foundry design rules and careful integration with peripheral circuitry. The bitcell array itself is fixed, but the surrounding design determines performance, power, and yield.
Core principles to remember:
- Bitcell Placement — The core array is fixed; never alter its geometry. Focus on precise integration with the periphery.
- Periphery vs. Core — Periphery devices (sense amps, write drivers, assist circuits) can use analog matching techniques, while the core must remain rule-driven.
- Routing for Performance — Keep bitlines and wordlines short and balanced to reduce skew and IR drop.
- Assist Circuits — Lay these out to minimize coupling into sensitive lines, maintaining symmetry for consistent performance.
- Custom vs. Compiler-Generated — Know how each integrates at top level and its impact on IR drop, skew, and verification.
Practical tip: Apply analog layout best practices to the periphery while treating the core as untouchable.
System-on-Chip (SoC) layout involves integrating multiple IP blocks into a unified design while meeting performance, power, and reliability targets. The challenge is balancing signal integrity, manufacturability, and complex physical constraints.
Core principles to remember:
- Hard IP Integration — Place sensitive analog and mixed-signal IPs (PLLs, LDOs, ADC/DACs) with adequate isolation from noisy digital regions.
- Power Grid Planning — Ensure robust strap placement and via density to minimize IR drop and electromigration risks across the chip.
- Clock & Reset Distribution — Design early for balanced clock tree and reset paths to avoid skew and timing closure surprises.
- I/O Ring & Padframe — Align pads for manufacturability and ESD protection while maintaining consistent pad-to-core routing.
- Verification Strategy — Plan for both block-level and top-level LVS/DRC from the outset to prevent integration bottlenecks.
Practical tip: Lock down power and clock distribution before fine-tuning signal routes.
These rules apply to all layout domains and form the foundation of good physical design. They help maintain performance, matching, and manufacturability across different process nodes.
Core principles to remember:
- Symmetry First — In matched devices, maintain mirrored geometry, routing, and surroundings to cancel out process gradients and stress effects.
- Layout Dependent Effects (LDE) — Control well proximity, STI stress, and diffusion effects by keeping device environments balanced.
See: Layout Dependent Effects (LDE) - Density & Dummy Devices — Use dummy gates, diffusion, and fill to meet local density targets and avoid CMP-induced variation.
- Shielding & Parasitics — Place grounded shields between sensitive nodes and aggressors; keep critical nets short to minimize coupling.
- Partitioning — Separate analog and digital regions to reduce substrate noise, clock interference, and thermal gradients.
- Floorplanning for Reliability — Consider electromigration, IR drop, and ESD paths early in the design to avoid last-minute redesigns.
Practical tip: If symmetry is broken, expect performance drift — fix it at layout, not in post-silicon debug.
Efficient layout work depends on knowing your tools, verifying early, and avoiding common late-stage issues.
Core principles to remember:
- Tool Mastery — Learn productivity shortcuts in Virtuoso and ICC2; configure views and layers to highlight rule-sensitive areas.
- Verification Workflow — Run LVS, DRC, and PEX incrementally instead of waiting until the end of a block or chip.
- EM/IR Awareness — Use analysis tools during layout, not just at sign-off, to catch early power and reliability issues.
- Automation — Use scripts or built-in automation to check repetitive layout patterns, density, and via rules.
- Peer Reviews — Have another layout engineer scan for symmetry, shielding, and spacing violations before formal verification.
Practical tip: Treat verification like layout’s second half — start it as soon as possible and run it often.