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Addressing Modes
Andreas Taylor edited this page Oct 18, 2025
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This is Version 2 of the CPU design.
Addressing modes define how instructions identify the operand(s) of each instruction.
See the Instructions wiki page to see which addressing modes are supported by each CPU instruction.
| Mode | Abbrev | Description |
|---|---|---|
| Immediate | IMM | Operand is a literal 4-bit value |
| Register Indirect | IND | Register contains the address of the operand |
| Register Direct | DIR | Operands are CPU registers, result is placed in register, no memory access |
| Implicit | IMP | Stack operations implicity use and update SP |
| Bit | BIT | Manipulate a specific bit within a register |
| Other | N/A | Instructions that don't have operands or an addressing mode |
Register Indirect and/or Indexed addressing modes may be supported at a future time, either by the Assembler or the CPU directly.
Direct mode is not supported due to the lack of available bits in the opcode.
| Date | Changes |
|---|---|
| 15-Oct-2025 | Created - Design Version 2 |
| 18-Oct-2025 | Optimizing the instruction set, better addressing mode grouping |